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CY7C1460BV25 cy7c1462bv25 36-mbit (1 m 36/2 m 18) pipelined sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-74446 rev. *c revised october 25, 2012 36-mbit (1 m 36/2 m 18) pipelined sram with nobl? architecture features pin-compatible and functionally equivalent to zbt? supports 250-mhz bus operations with zero wait states ? available speed grades is 250 mhz internally self-timed output buffe r control to eliminate the need to use asynchronous oe fully registered (inputs and outputs) for pipelined operation byte write capability 2.5 v core power supply 2.5 v/1.8 v i/o power supply fast clock-to-output times ? 2.6 ns (for 250-mhz device) clock enable (cen ) pin to suspend operation synchronous self-timed writes CY7C1460BV25, cy7c1462bv25 available in pb-free 165-ball fbga package and cy7c1462bv25 available in jedec-standard pb-free 100-pin tqfp package ieee 1149.1 jtag-compatible boundary scan burst capability ? linear or interleaved burst order ?zz? sleep mode option and stop clock option functional description the CY7C1460BV25/cy7c1462bv25 are 2.5 v, 1 m 36/2 m 18 synchronous pipelined burst srams with no bus latency? (nobl ?? logic, respectively. they are designed to support unlimited true back-to -back read/write operations with no wait states. the CY7C1460BV25/cy7c1462bv25 are equipped with the advanced nobl logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the throughput of data in systems that require frequent write/read transitions. the CY7C1460BV25/cy7c1462bv25 are pin-compatible and functionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation an d extends the previous clock cycle. write operations are controlled by the byte write selects (bw a ?bw d for CY7C1460BV25 and bw a ?bw b for cy7c1462bv25) and a write enable (we ) input. all writes are conducted with on-chip synchron ous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state control. in order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. logic block diagram ? CY7C1460BV25 a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e clk cen write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 2 of 30 logic block diagram ? cy7c1462bv25 a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk cen write drivers zz sleep control
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 3 of 30 contents selection guide ................................................................ 4 pin configurations ........................................................... 4 pin definitions .................................................................. 6 functional overview ........................................................ 7 single read accesses ................................................ 7 burst read accesses .................................................. 7 single write accesses ................................................. 7 burst write accesses .................................................. 8 sleep mode ................................................................. 8 interleaved burst address tabl e ................................. 8 linear burst address table ......................................... 8 zz mode electrical characteri stics .............................. 8 truth table ........................................................................ 9 partial write cycle description ..................................... 10 partial write cycle description ..................................... 11 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 12 disabling the jtag feature ...................................... 12 test access port (tap) ............................................. 12 performing a tap r eset .......... .............. .......... 12 tap registers ...................................................... 12 tap instruction set ................................................... 12 tap controller state diagram ....................................... 14 tap controller block diagram ...................................... 15 tap timing ...................................................................... 15 tap ac switching characteristics ............................... 16 2.5 v tap ac test conditions ....................................... 17 2.5 v tap ac output load equivalent ......................... 17 1.8 v tap ac test conditions ....................................... 17 1.8 v tap ac output load equivalent ......................... 17 tap dc electrical characteristics and operating conditions ..................................................... 17 identification register definitions ................................ 18 scan register sizes ....................................................... 18 instruction codes ........................................................... 18 boundary scan order .................................................... 19 maximum ratings ........................................................... 20 operating range ............................................................. 20 electrical characteristics ............................................... 20 capacitance .................................................................... 21 thermal resistance ........................................................ 21 ac test loads and waveforms ..................................... 21 switching characteristics .............................................. 22 switching waveforms .................................................... 23 ordering information ...................................................... 25 ordering code definitions ..... .................................... 25 package diagrams .......................................................... 26 acronyms ........................................................................ 28 document conventions ................................................. 28 units of measure ....................................................... 28 document history page ................................................. 29 sales, solutions, and legal information ...................... 30 worldwide sales and design s upport ......... .............. 30 products .................................................................... 30 psoc solutions ......................................................... 30
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 4 of 30 selection guide description 250 mhz unit maximum access time 2.6 ns maximum operating current 435 ma maximum cmos standby current 120 ma pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout a a a a a 1 a 0 v ss v dd a a a a a a a nc nc v ddq v ss nc dqpa dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb v dd v ss dqb dqb v ddq v ss dqb dqb dqpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode cy7c1462bv25 (2 m 18) nc nc nc/288m nc/144m nc/72m a a
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 5 of 30 figure 2. 165-ball fbga (15 17 1.4 mm) pinout pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g dqp c dq c dqp d nc dq d a ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/72m v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc oe a a nc v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g nc nc dqp b nc dq b a ce 1 ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc nc/72m v ddq bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc a oe a a v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a cy7c1462bv25 (2 m 18) CY7C1460BV25 (1 m 36) a a nc nc
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 6 of 30 pin definitions pin name i/o type pin description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a , bw b , bw c , bw d input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst count er is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dq a , dq b, dq c , dq d i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, t hey deliver the data contained in t he memory location specified by a x during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq d are placed in a tri-state condition. the outputs ar e automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp a, dqp b, dqp c, dqp d i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq [31:0] . during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d . mode input strap pin mode input . selects the burst order of the device. tied hi gh selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states durin g operation. when left floating mode will default high, to an interleaved burst order. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. tms test mode select synchronous this pin controls the test access port state machine . sampled on the rising edge of tck. tck jtag-clock clock input to the jtag circuitry .
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 7 of 30 functional overview the CY7C1460BV25/cy7c1462bv25 are synchronous-pipelined burst nobl srams designed specifically to eliminate wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access dela y from the clock rise (t co ) is 2.6 ns (250-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write oper ation, depending on the status of the write enable (we ). bw [x] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on- chip synchronous self-t imed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and de selects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent operation (read/write/ deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. burst read accesses the CY7C1460BV25/cy7c1462bv25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read accesses section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incremented sufficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address inputs is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise t he data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d /dqp a,b,c,d for CY7C1460BV25 and dq a,b /dqp a,b for cy7c1462bv25). in addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . should be connected to ground of the system. nc n/a no connects . this pin is not connected to the die. nc/72m n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. nc /576m n/a not connected to the die . can be tied to any voltage level. nc /1g n/a not connected to the die . can be tied to any voltage level. zz input- asynchronous zz ?sleep? input . this active high input plac es the device in a non-time critical ?sleep? condition with data integrity preserved. during normal operation, th is pin has to be low or left floating. zz pin has an internal pull-down. pin definitions (continued) pin name i/o type pin description
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 8 of 30 on the next clock rise the data presented to dq and dqp (dq a,b,c,d /dqp a,b,c,d for CY7C1460BV25 and dq a,b /dqp a,b for cy7c1462bv25) (or a subset fo r byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the writ e operation is controlled by bw (bw a,b,c,d for CY7C1460BV25 and bw a,b for cy7c1462bv25) signals. the CY7C1460BV25/cy7c1462bv25 provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bw ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a syn chronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the CY7C1460BV25/cy7c1462bv25 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dqp ( dq a,b,c,d /dqp a,b,c,d for CY7C1460BV25 and dq a,b /dqp a,b for cy7c1462bv25) inputs. doing so will tri-state the output drivers. as a safety precaution, dq and dqp (dq a,b,c,d /dqp a,b,c,d for CY7C1460BV25 and dq a,b /dqp a,b for cy7c1462bv25) are automatically three-stated durin g the data portion of a write cycle, regardless of the state of oe . burst write accesses the CY7C1460BV25/cy7c1462bv25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write accesses section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw ( bw a,b,c,d for CY7C1460BV25 and bw a,b for cy7c1462bv25) inputs must be driven in each cycl e of the burst write in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz ? v dd ?? 0.2 v ? 100 ma t zzs device operation to zz zz ?? v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz ? 0.2 v 2t cyc ?ns t zzi zz active to sleep current t his parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ? ns
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 9 of 30 truth table the truth table for CY7C1460BV25/cy7c1462bv25 follows. [1, 2, 3, 4, 5, 6, 7] operation address used ce zz adv/ld we bw x oe cen clk dq deselect cycle none h l l x x x l l?h tri-state continue deselect cycle none x l h x x x l l?h tri-state read cycle (begin burst) external l l l h x l l l?h data out (q) read cycle (continue burst) n ext x l h x x l l l?h data out (q) nop/dummy read (begin burst) e xternal l l l h x h l l?h tri-state dummy read (continue burst) next x l h x x h l l?h tri-state write cycle (begin burst) external l l l l l x l l?h data in (d) write cycle (continue burst) next x l h x l x l l?h data in (d) nop/write abort (begin burst) none l l l l h x l l?h tri-state write abort (continue burst) next x l h x h x l l?h tri-state ignore clock edge (stall) current x l x x x x h l?h ? sleep mode none x h x x x x x x tri-state notes 1. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 2. write is defined by we and bw x . see write cycle description table for details. 3. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 4. the dq and dqp pins are controlled by the current cycle and the oe signal. 5. cen = h inserts wait states. 6. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dq s and dqp x = three-state when oe is inactive or when the device is deselected, and dq s =data when oe is active.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 10 of 30 partial write cycle description the partial write cycle description table for CY7C1460BV25 follows. [8, 9, 10, 11] function (CY7C1460BV25) we bw d bw c bw b bw a read h x x x x write ? no bytes written l h h h h write byte a ? (dq a and dqp a )lhhhl write byte b ? (dq b and dqp b )lhhlh write bytes b, a l h h l l write byte c ? (dq c and dqp c )lhlhh write bytes c, a l h l h l write bytes c, b l h ll l h write bytes c, b, a l h l l l write byte d ? (dq d and dqp d )llhhh write bytes d, a l l h h l write bytes d, b l l h l h write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes lllll notes 8. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 9. write is defined by we and bw x . see write cycle description table for details. 10. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 11. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 11 of 30 partial write cycle description the partial write cycle description table for cy7c1462bv25 follows. [12, 13, 14, 15] function (cy7c1462bv25) we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l notes 12. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 13. write is defined by we and bw x . see write cycle description table for details. 14. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 15. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 12 of 30 ieee 1149.1 serial boundary scan (jtag) the CY7C1460BV25/cy7c1462bv25 incorporates a serial boundary scan test access port (tap). this part is fully compliant with 1149.1. the tap operates using jedec-standard 2.5 v/1.8 v i/o logic level. the CY7C1460BV25/cy7c1462bv25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low(v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which wil l not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller block diagram on page 15 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) of any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state diagram on page 14 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset in ternally to ensure that tdo comes up in a high z state. tap registers registers are connected betwe en the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 15 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the length of the boundary scan register for the sram in different packages is listed in the scan register sizes table. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order on page 19 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identification register definitions on page 18 . tap instruction set overview eight different instructions are possible with the three bit instruction register . all combinations are listed in the instruction codes on page 18 . three of these instru ctions are listed as reserved and should not be used. the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 13 of 30 tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1-mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to th e value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap co ntroller?s capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preloa d instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck an d ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required ? that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system ou tput pins. this inst ruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #89 (for 165-ball fbga package). wh en this scan cell, called the ?extest output bus tri-st ate,? is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instructio n. when high, it will enable the output buffers to drive the ou tput bus. when low, this bit will place the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? state. during ?update-dr,? the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bus pins. note that this bit is preset high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 14 of 30 tap controller state diagram the 0/1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 15 of 30 tap controller block diagram tap timing bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck tms tap controller tdi tdo t tl test clock (tck) 123456 test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 16 of 30 tap ac switchi ng characteristics over the operating range parameter [16, 17] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns set-up times t tmss tms set-up to tck clock rise 5 ? ns t tdis tdi set-up to tck clock rise 5 ? ns t cs capture set-up to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 16. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 17. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 17 of 30 2.5 v tap ac test conditions input pulse levels ...............................................v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ..... .................... ..............1.25 v output reference levels .............................................. 1.25 v test load termination supply voltage .......................... 1.25 v 2.5 v tap ac out put load equivalent 1.8 v tap ac test conditions input pulse levels ............ .................... 0.2 v to v ddq ? 0.2 v input rise and fall time ....................................................1 ns input timing reference levels ... ...................................... 0.9 v output reference levels ................................................ 0.9 v test load termination supply vo ltage ............................ 0.9 v 1.8 v tap ac output load equivalent tdo 1.25v 20pf z = 50 ? o 50 ? tdo 0.9v 20pf z = 50 ? o 50 ? (0 c < t a < +70 c; v dd = 2.5 v 0.125 v unless otherwise noted) parameter [18] description test conditions min max unit v oh1 output high voltage i oh = ?1.0 ma v ddq = 2.5 v 1.7 ? v v oh2 output high voltage i oh = ?100 ? av ddq = 2.5 v 2.1 ? v v ddq = 1.8 v 1.6 ? v v ol1 output low voltage i ol = 1.0 ma v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 ? av ddq = 2.5 v ? 0.2 v v ddq = 1.8 v ? 0.2 v v ih input high voltage v ddq = 2.5 v 1.7 v dd + 0.3 v v ddq = 1.8 v 1.26 v dd + 0.3 v v il input low voltage v ddq = 2.5 v ?0.3 0.7 v v ddq = 1.8 v ?0.3 0.36 v i x input load current gnd ? v i ? v ddq ?5 5 ? a note 18. all voltages referenced to v ss (gnd).
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 18 of 30 identification regi ster definitions instruction field CY7C1460BV25 (1 m 36) cy7c1462bv25 (2 m 18) description revision number (31:29) 000 000 describes the version number device depth (28:24) 01011 01011 reserved for internal use architecture/memory type(23:18) 001000 001000 defines memory type and architecture bus width/density(17:12) 100111 010111 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 a llows unique identification of sram vendor id register presence indicator (0) 1 1 indicates the presence of an id register scan register sizes register name bit size ( 36) bit size ( 18) instruction 3 3 bypass 11 id 32 32 boundary scan order (165-ball fbga package) 89 89 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places th e boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 19 of 30 boundary scan order 165-ball fbga [19] CY7C1460BV25 (1 m 36), cy7c1462bv25 (2 m 18) bit# ball id bit# ball id bit# ball id bit# ball id 1n6 26e11 51a3 76n1 2n7 27d11 52a2 77n2 3n10 28g10 53b2 78p1 4p11 29f10 54c2 79r1 5 p8 30 e10 55 b1 80 r2 6 r8 31 d10 56 a1 81 p3 7r9 32c11 57c1 82r3 8p9 33a11 58d1 83p2 9p10 34b11 59e1 84r4 10 r10 35 a10 60 f1 85 p4 11 r11 36 b10 61 g1 86 n5 12h11 37a9 62d2 87p6 13 n11 38 b9 63 e2 88 r6 14 m11 39 c10 64 f2 89 internal 15 l11 40 a8 65 g2 16 k11 41 b8 66 h1 17 j11 42 a7 67 h3 18 m10 43 b7 68 j1 19 l10 44 b6 69 k1 20 k10 45 a6 70 l1 21 j10 46 b5 71 m1 22 h9 47 a5 72 j2 23 h10 48 a4 73 k2 24 g11 49 b4 74 l2 25 f11 50 b3 75 m2 note 19. bit# 89 is preset high.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 20 of 30 maximum ratings exceeding maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +3.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc to outputs in tri-state ...................?0.5 v to v ddq + 0.5 v dc input voltage .............. .............. ..... ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) ........... ............... > 2001v latch-up current ................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 2.5 v ? 5% / + 5% 1.7 v to v dd electrical characteristics over the operating range parameter [20, 21] description test conditions min max unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage for 2.5 v i/o 2.375 v dd v for 1.8 v i/o 1.7 1.9 v v oh output high voltage for 2.5 v i/o, i oh = ?? 1.0 ma 2.0 ? v for 1.8 v i/o, i oh = ?100 ? a1.6?v v ol output low voltage for 2.5 v i/o, i ol = ? 1.0 ma ? 0.4 v for 1.8 v i/o, i ol = 100 ? a?0.2v v ih input high voltage [20] for 2.5 v i/o 1.7 v dd + 0.3 v for 1.8 v i/o 1.26 v dd + 0.3 v v il input low voltage [20] for 2.5 v i/o ?0.3 0.7 v for 1.8 v i/o ?0.3 0.36 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz ?435ma i sb1 automatic ce power-down current ? ttl inputs max v dd , device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 4-ns cycle, 250 mhz ?185ma i sb2 automatic ce power-down current ? cmos inputs max v dd , device deselected, v in ? 0.3 v or v in > v ddq ?? 0.3 v, f = 0 4-ns cycle, 250 mhz ?120ma notes 20. overshoot: v ih(ac) < v dd +1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 21. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 21 of 30 i sb3 automatic ce power-down current ? cmos inputs max v dd , device deselected, v in ? 0.3 v or v in > v ddq ?? 0.3 v, f = f max = 1/t cyc 4-ns cycle, 250 mhz ?160ma i sb4 automatic ce power-down current ? ttl inputs max v dd , device deselected, v in ? v ih or v in ? v il , f = 0 4-ns cycle, 250 mhz ?135ma capacitance parameter [22] description test conditions 100-pin tqfp max 165-ball fbga max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5 v v ddq = 2.5 v 6.5 7 pf c clk clock input capacitance 3 7 pf c i/o input/output capacitance 5.5 6 pf thermal resistance parameter [22] description test conditions 100-pin tqfp package 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 25.21 20.8 c/w ? jc thermal resistance (junction to case) 2.58 3.2 c/w ac test loads and waveforms figure 3. ac test loads and waveforms electrical characteristics (continued) over the operating range parameter [20, 21] description test conditions min max unit output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load note 22. tested initially and after any design or process change that may affect these parameters.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 22 of 30 switching characteristics over the operating range parameter [23, 24] description -250 unit min max t power [25] v cc (typical) to the first access read or write 1 ? ms clock t cyc clock cycle time 4.0 ? ns f max maximum operating frequency ? 250 mhz t ch clock high 1.5 ? ns t cl clock low 1.5 ? ns output times t co data output valid after clk rise ? 2.6 ns t eov oe low to output valid ? 2.6 ns t doh data output hold after clk rise 1.0 ? ns t chz clock to high z [26, 27, 28] ? 2.6 ns t clz clock to low z [26, 27, 28] 1.0 ? ns t eohz oe high to output high z [26, 27, 28] ? 2.6 ns t eolz oe low to output low z [26, 27, 28] 0 ? ns set-up times t as address set-up before clk rise 1.2 ? ns t ds data input set-up before clk rise 1.2 ? ns t cens cen set-up before clk rise 1.2 ? ns t wes we , bw x set-up before clk rise 1.2 ? ns t als adv/ld set-up before clk rise 1.2 ? ns t ces chip select set-up 1.2 ? ns hold times t ah address hold after clk rise 0.3 ? ns t dh data input hold after clk rise 0.3 ? ns t cenh cen hold after clk rise 0.3 ? ns t weh we , bw x hold after clk rise 0.3 ? ns t alh adv/ld hold after clk rise 0.3 ? ns t ceh chip select hold after clk rise 0.3 ? ns notes 23. timing reference is 1.25 v when v ddq = 2.5 v and 0.9 v when v ddq = 1.8 v. 24. test conditions shown in (a) of figure 3 on page 21 unless otherwise noted. 25. this part has a voltage regulator internally; t power is the time power needs to be supplied above v dd(minimum) initially, before a read or write operation can be initiated. 26. t chz , t clz , t eolz , and t eohz are specified with ac test conditions shown in (b) of figure 3 on page 21 . transition is measured 200 mv from steady-state voltage. 27. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect param eters guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 28. this parameter is sampled and not 100% tested.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 23 of 30 switching waveforms figure 4. read/write/timing [29, 30, 31] figure 5. nop, stall and deselect cycles [29, 30, 32] write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data in-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh don?t care undefined q(a6) q(a4+1) read q(a3) 456 78910 clk ce we cen bwx adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a2 d(a1) q(a2) q(a3) notes 29. for this waveform zz is tied low. 30. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 31. order of the burst sequence is determined by the status of th e mode (0=linear, 1=interleaved). burst operations are optional . 32. the ignore clock edge or stall cycle (clock 3) illustrated cen being used to create a pause. a write is not performed during this cycle.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 24 of 30 figure 6. zz mode timing [33, 34] switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 33. device must be deselected when entering zz mode. see cycle desc ription table for all possible signal conditions to deselect the device. 34. i/os are in high z when exiting zz sleep mode.
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 25 of 30 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations an d features. the below table contains o nly the list of parts that are currently av ailable.for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 250 CY7C1460BV25-250bzxc 51-85165 165-ball fbga (15 17 1.4 mm) pb-free commercial cy7c1462bv25-250bzxc 51-85165 165-ball fbga (15 17 1.4 mm) pb-free cy7c1462bv25-250axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free temperature range: c = commercial = 0 c to +70 c x = pb-free package type: xx = bz or a bz = 165-ball fbga a = 100-pin tqfp speed grade: 250 mhz v25 = 2.5 v v dd process technology: b ? 90 nm part identifier: 146x = 1460 or 1462 1460 = pl, 1 mb 36 (36 mb) 1462 = pl, 2 mb 18 (36 mb) technology code: c = cmos marketing code: 7 = srams company id: cy = cypress c 146x b - 250 c xx v25 x cy 7
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 26 of 30 package diagrams figure 7. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 27 of 30 figure 8. 165-ball fbga (15 17 1.4 mm) (0.45 ball diameter) package outline, 51-85165 package diagrams (continued) 51-85165 *d
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 28 of 30 acronyms document conventions units of measure acronym description ce chip enable cen clock enable cmos complementary metal-oxide-semiconductor eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group lsb least significant bit msb most significant bit nobl no bus latency oe output enable sram static random access memory tap test access port tck test clock tms test mode select tdi test data-in tdo test data-out tqfp thin quad flat pack ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt ns nanosecond % percent pf picofarad vvolt wwatt
CY7C1460BV25 cy7c1462bv25 document number: 001-74446 rev. *c page 29 of 30 document history page document title: CY7C1460BV25/cy7c1462bv25, 36-mbit (1 m 36/2 m 18) pipelined sram with nobl? architecture document number: 001-74446 rev. ecn no. issue date orig. of change description of change ** 3457582 12/07/2011 prit new data sheet. *a 3531263 02/21/2012 prit changed stat us from preliminary to final. *b 3747489 09/18/2012 prit updated features (included CY7C1460BV25 related information, included 165-ball fbga package related information). updated functional description (included CY7C1460BV25 related information). added logic block diagram ? CY7C1460BV25 . updated pin configurations (included CY7C1460BV25 related information). updated pin definitions (included jtag related information). updated functional overview (included CY7C1460BV25 related information). updated truth table (included CY7C1460BV25 related information). added partial write cycle description (corresponding to CY7C1460BV25). added ieee 1149.1 serial boundary scan (jtag) . added tap controller state diagram . added tap controller block diagram . added tap timing . added tap ac switching characteristics . added 2.5 v tap ac te st conditions . added 2.5 v tap ac output load equivalent . added 1.8 v tap ac te st conditions . added 1.8 v tap ac output load equivalent . added tap dc electrical characteristics and operating conditions . added identification register definitions . added scan register sizes . added instruction codes . added boundary scan order . updated operating range (removed industrial temperature range). updated ordering information (updated part numbers). updated package diagrams (included 165-ball fbga package related information (spec 51-85165)). *c 3793924 10/25/2012 prit no technical updates. completing sunset review.
document number: 001-74446 rev. *c revised october 25, 2012 page 30 of 30 zbt is a registered trademark of integrated device technology, inc. no bus latency and nobl are trademarks of cypress semicondu ctor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1460BV25 cy7c1462bv25 ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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